This disclosure relates to analog to digital conversion circuits that interleave a plurality of analog-to-digital (AD) converters to improve total sampling rates and include filters to correct errors in sampling timings of the AD converters.
<First Conventional Art>
Time-interleaved AD conversion systems having improved total sampling rates by interleaving a plurality of AD converters, which sample an analog signal at different timings, are known. It is further proposed to correct errors in the interleaving operation by providing correction filters corresponding to respective AD converters in, for example, US patent publication No. US 2004/032358 (Patent document 1). The correction filter has a function of recovering a value that is supposed to be sampled, and stores coefficient corresponding to timing errors to be corrected.
<Second Conventional Art>
In addition, for example, US patent publication No. US 2003/058144 (Patent document 2) proposes to provide a finite impulse response (FIR) type correction filter having two input terminals and output terminals. The FIR filter outputs an output of one of the AD converters after a delay from one of the output terminals. The FIR filter further outputs, from the other one of the output terminals, a signal generated by processing the output signals of the AD converters input to both of the input terminals. Finally a multiplexer interleaves, or alternately outputs, two output signals of the FIR filter.
The correction filter of the first conventionally art, which has a function to recover a value that is supposed to be sampled, may be constructed as show in FIG. 8. This is so-called Fractional Delay Filter, which has impulse responses shown in FIG. 1 when the number of taps NT (or the number of multipliers) is 7.
When the number of AD converters is 2, outputs of AD converters are interleaved after processing an output of one of the converters by a correction filter of the characteristic show in FIG. 1 and delaying an output of the other one of the converters by a delay circuit for a timing adjustment. The filter characteristic of the correction filter is set to the characteristic of Δt=0 if there is no error Δt in the sampling timings of two AD converters. When there is an error, the filter characteristic is set to the characteristic of, for example, Δt=0.5 TS′. TS′ is equal to 0.5 TS, and TS represents the sampling period of each AD converter.
In the first conventional art, it is necessary to supply clock signals with successively different phases to the plurality of AD converters to control timings that respective converters sample the analogue signal. It is also necessary to supply clock signals with successively different phases to the correction filters corresponding to respective AD converters. Thus, because it is necessary to supply multiphase clock signals to both the AD converters and correction filters, the timing design of the semiconductor integrated circuit that equipped with these blocks becomes complex.
Moreover, as explained above, the correction filter has a construction that stores coefficients corresponding to error values to be corrected in a storage block beforehand. However, in actual AD conversion circuits, the error value is different for each product due to variation in the delay time of buffers in the clock supply route and varies with, for example, the power supply voltage and temperature. Therefore, in order to store a large number of coefficients corresponding to a variety of error values, a large memory block is required. Alternatively, it would be possible to measure an actual error value and generate a coefficient corresponding to the measured error value by using an arithmetic circuit. In this case, however, it is necessary to integrate a complicated arithmetic circuit in a semiconductor integrated circuit.
The second conventional art also has a problem that it is necessary to supply multi-phase clock signal to the correction filter, and the timing design becomes complex. There is an additional problem that storing a large number of coefficients corresponding to various error values or providing an arithmetic circuit to generate the coefficients is required.
It would be advantageous to provide time-interleaved AD conversion circuits that are capable to conduct timing designs easily. It would be further advantageous to provide time-interleaved AD converters having correction filters that can correct various values of sampling timing errors without requiring large memory blocks or complicated arithmetic circuits.